Preceding sentence, the isync instruction may complete before storageĪccesses associated with instructions preceding the >From the isync description in the ISA: "Except as described in the Rather than a storage instruction, should be fully ordered by isync. The twi, being a flow control instruction The data (not date) dependency means that the twi will not execute untilĪfter the load instruction returns data (thus, after the device has > is no intention to order the storage access? > wondering why we need to order the load and the following delay loop if there > instructions can execute out of order, but complete in order. > Why do we need the 'date dependency' here? According to the e6500 manual, the > order the delay loop after the load, the following sequence should be enough: It only talks about when accesses "to memory regions affectedīy the configuration register write" can be safely made.
ISYNC SOFTWARE MANUAL
If you're referring to the section you quoted above, the manual does not > The sequence "write, readback, sync" will guarantee this according to the manual. > does really take effect before we begin to delay loop. > I think the point is to make sure that the writing of the CCSR_DDR_SDRAM_CFG_2 > The point is to order the delay loop after the load, not to order > According to the PowerISA, the sequence 'load, date dependency, isync' only > accessors used from C code, orders the readback versus all future
ISYNC SOFTWARE PLUS
> The data dependency plus isync sequence, which is done by the normal I/O > finished the transaction to the point of acting on another one. > make sure the device has seen the write, ensuring that the device has > comment near the end of fsl_elbc_write_buf() in > sure that the writing to CCSR register does really take effect. > The 'write, readback, sync' is the required sequence if we want to make > No, we don't just want to order the subsequent memory access here. > with subsequent memory accesses, though in that case wouldn't a sync > A sync after the readback helps if you're trying to order the readback > since transactions to the same address should already be ordered. > I agree that the sync before the readback is probably not necessary, > regions affected by the configuration register write. Then accesses can safely be made to memory > immediately followed by a read of the same register, and that should be > registers are in effect, the final configuration register write should be > To guarantee that the results of any sequence of writes to configuration > Shouldn't we use "readback, sync" here? The following is quoted form t4240RM:
Subject: Re: powerpc/pm: support deep sleep feature on T1040ĭate: Tue, 18:18:54 -0500
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Re: powerpc/pm: support deep sleep feature on T1040 - Scott Wood LKML Archive on help / color / mirror / Atom feed From: Scott Wood
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